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ON Semiconductort
The MC74VHCT04A is an advanced high speed CMOS inverter fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems. The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3V to 5.0V, because it has full 5V CMOS level output swings. The VHCT04A input structures provide protection when voltages between 0V and 5.5V are applied, regardless of the supply voltage. The output structures also provide protection when VCC = 0V. These input and output structures help prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc. * High Speed: tPD = 4.7ns (Typ) at VCC = 5V * Low Power Dissipation: ICC = 2A (Max) at TA = 25C * TTL-Compatible Inputs: VIL = 0.8V; VIH = 2.0V * Power Down Protection Provided on Inputs and Outputs * Balanced Propagation Delays * Designed for 4.5V to 5.5V Operating Range * Low Noise: VOLP = 1.0V (Max) * Pin and Function Compatible with Other Standard Logic Families * Latchup Performance Exceeds 300mA * ESD Performance: HBM > 2000V; Machine Model > 200V * Chip Complexity: 48 FETs or 12 Equivalent Gates
Hex Inverter
MC74VHCT04A
D SUFFIX 14-LEAD SOIC PACKAGE CASE 751A-03
DT SUFFIX 14-LEAD TSSOP PACKAGE CASE 948G-01
M SUFFIX 14-LEAD SOIC EIAJ PACKAGE CASE 965-01 ORDERING INFORMATION MC74VHCTXXAD MC74VHCTXXADT MC74VHCTXXAM SOIC TSSOP SOIC EIAJ
FUNCTION TABLE
Inputs A L H Outputs Y H L
w
These devices are available in Pb-free package(s). Specifications herein apply to both standard and Pb-free devices. Please see our website at www.onsemi.com for specific Pb-free orderable part numbers, or contact your local ON Semiconductor sales office or representative.
1 3 5 9 11 13 2 4 6 8 10 12
A1 A2 A3 A4 A5 A6
Y1 Y2 Y3 Y=A Y4 Y5 Y6 1 A1 2 Y1 3 A2 4 Y2 5 A3 6 Y3 7 GND VCC 14 A6 13 Y6 12 A5 11 Y5 10 A4 9 Y4 8
Figure 1. Logic Diagram
Figure 2. Pinout: 14-Lead Packages (Top View)
(c) Semiconductor Components Industries, LLC, 2006
March, 2006 - Rev. 3
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Publication Order Number: MC74VHCT04A/D
II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I II II I II II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I II II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIII I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I IIII I II I I I I I I I IIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I II II I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I III II I I I I I I I I II II I I II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I III I I II II II II I II IIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Derating -- SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
III I I I I I I I I I I IIIIIIIIIIIII III I I I I I IIIIIIIIIIIII III I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I IIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII I I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I IIIIIIIIIIIII III I I I I I IIIIIIIIIIIII III I I I I I I I I I I I I IIIIIIIIIIIII III I I I I I IIIIIIIIIIIII III I I I I I I I I I IIIIIIIIIIIIIIII IIII IIIIIII I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
SymbolIIIIIIIIIIIIII Parameter VCC Vout Tstg ICC IOK Iout Vin PD IIK Storage Temperature Power Dissipation in Still Air, DC Supply Current, VCC and GND Pins DC Output Current, per Pin Output Diode Current (VOUT < GND; VOUT > VCC) Input Diode Current DC Output Voltage DC Input Voltage DC Supply Voltage SOIC Packages TSSOP Package VCC = 0 High or Low State - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 65 to + 150 - 0.5 to + 7.0III V - 0.5 to + 7.0III V Value - 20 50 25 20 500 450 Unit mW mA mA mA mA _C V
DC ELECTRICAL CHARACTERISTICS
RECOMMENDED OPERATING CONDITIONS
Symbol
Symbol
IOPD
ICCT
VOH
VOL
VCC
Vout
VIH
ICC
tr, tf
VIL
Vin
TA
Iin
Output Leakage Current
Quiescent Supply Current
Maximum Quiescent Supply Current
Maximum Input Leakage Current
Maximum Low-Level Output Voltage Vin = VIH or VIL
Minimum High-Level Output Voltage Vin = VIH or VIL
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
Input Rise and Fall Time
Operating Temperature
DC Output Voltage
DC Input Voltage
DC Supply Voltage
Parameter
VOUT = 5.5V
Per Input: VIN = 3.4V Other Input: VCC or GND
Vin = VCC or GND
Vin = 5.5 V or GND
Test Conditions
IOH = - 50A
IOH = - 8mA
IOL = 50A
IOL = 8mA
VCC = 0 High or Low State
VCC =5.0V 0.5V
Parameter
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0 to 5.5 4.5 to 5.5 4.5 to 5.5 VCC V 5.5 5.5 4.5 4.5 4.5 4.5 0
2 3.94 Min 4.4 2.0 TA = 25C Typ 0.0 4.5 0.1 1.35 0.36 Max 2.0 0.1 0.8 0.5 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. TA = - 40 to 85C 3.80 Min 4.4 2.0 - 40 Min 4.5 0 0 0 0 1.0 1.50 20.0 0.44 Max 0.1 0.8 5.0 + 85 Max 5.5 VCC 5.5 5.5 20 ns/V Unit Unit mA A A _C V V V V V V V A
II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIII II II I I II I I II IIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I I I I I I I I I I I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
Symbol tPLH, tPHL Cin Parameter TA = 25C Typ 4.7 5.5 4 TA = - 40 to 85C Min 1.0 1.0 Max 7.5 8.5 10 Test Conditions Min Max 6.7 7.7 10 Unit ns Maximum Propagation Delay, A to Y VCC = 5.0 0.5V CL = 15pF CL = 50pF Maximum Input Capacitance pF Typical @ 25C, VCC = 5.0V 11 CPD Power Dissipation Capacitance (Note 1) pF 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC/6 (per buffer). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
TA = 25C Symbol VOLP VOLV VIHD VILD Characteristic Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Typ 0.8 -0.8 Max 1.0 -1.0 2.0 0.8 Unit V V V V
TEST POINT A 3V 1.5V GND tPLH Y 1.5V tPHL VOH VOL *Includes all probe and jig capacitance DEVICE UNDER TEST OUTPUT CL*
Figure 3. Switching Waveforms
Figure 4. Test Circuit
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OUTLINE DIMENSIONS D SUFFIX SOIC-14 CASE 751A-03 ISSUE F
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
-A-
14 8
-B-
1 7
P 7 PL 0.25 (0.010)
M
B
M
G
C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
M
K TB
S
M A
S
J
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
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OUTLINE DIMENSIONS DT SUFFIX TSSOP CASE 948G-01 ISSUE O
14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V N
S
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
0.15 (0.006) T U
S
A -V-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
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EEC CC EEC CC
SECTION N-N -W-
OUTLINE DIMENSIONS M SUFFIX SO-14 CASE 965-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056
14
8
LE Q1 E HE M_ L DETAIL P
1
7
Z D e A VIEW P
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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Notes
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